Generally, the on resistance of vertical power MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) is strongly dependent on the electrical resistance of the drift layer. If the impurity concentration is raised to lower the electrical resistance of the drift layer, the withstand voltage at the p-n junction interface between the base layer and the drift layer is reduced. Thus, there is a tradeoff between having a low on resistance and withstand voltage. To improve the tradeoff a super junction structure is used in which multiple n-type semiconductor layers and p-type semiconductor layers are arranged in the drift layer. In the super junction structure, a quantity of p-type impurities in the p-type semiconductor layer and a quantity of n-type impurities in the n-type semiconductor layer are arranged to be equal. Hence, even if the p-type and n-type impurity concentrations are high, the drift layer is fully depleted, and the high withstand voltage can be maintained. Further, to lower the on resistance, a structure is used whereby the p-type semiconductor layer is formed to be columnar within the super junction structure, and an island-like p-type base layer is formed a top portion thereof. In the structure, the channel density is increased by forming a lattice-form, offset lattice-form, or honeycomb-form gate electrode bridging among the island-like p-type base layers, and a low on resistance can thus be realized. However, since the p-type base layer and the n-type source layers are electrically connected via an opening of the gate electrode, the effects of contact defects between the p-type base layer and the source electrode increase as miniaturization proceeds. Consequently, discharge of electron holes to the source electrode at avalanche breakdown is suppressed and avalanche resistance is reduced.